Complex digital data circuits use various architectures to distribute data signals between multiple locations. A digital crosspoint switch can selectably connect data signals between multiple inputs and multiple outputs. One way to implement a crosspoint switch is as an array of multiplexer stages. For example, a 32×32 crosspoint switch can be implemented as an array of thirty-two 32:1 multiplexers which share a 32-input bus.
FIG. 1 shows the functional block architecture of a typical crosspoint switch. The left edge of the figure shows inputs 0–39 and the bottom edge shows outputs 0–35. Any input can be connected to any number of outputs. Each of the smaller dashed line boxes along the left side of FIG. 1 represents a two-stage input buffer. The larger dashed line boxes in the center of the figure are arrays of point cells to connect a selected input to a selected output. The smaller dashed line boxes along the bottom side of the figure are two-stage multiplexers to selectably connect multiple data paths to a given output port. As shown in FIG. 1, each of the second stage input buffers and first stage output multiplexers may serve only a subset of the output and input ports respectively. In addition, at high data speeds above 1 Gb/sec, the crosspoint may be further timesliced using parallel paths into alternating data slices at half the data rate each.
FIG. 2 provides a slice of such a crosspoint switch showing a single path connecting one input port to one output port. The crosspoint switch can be conceptually divided into a high-speed data path (shown by thin lines in FIG. 2) and a lower-speed control plane that determines connectivity (shown by thick lines in FIG. 2). The control plane is run by a digital clocking signal and determines which pieces of the data path should be enabled for a given connectivity and when the enabling signals should change. For the switch control plane, connectivity data to control the data path may be written into control latches or flip-flops.
In FIG. 2, the first stage buffer 21 provides a high impedance input (with reduced input capacitance) and converts signal levels, for example, from CMOS to current mode logic (CML). Driving four sets of input lines from each of the second stage input buffers 22 reduces the number of point cells 23 loading each input by a factor of four (only nine point cells 23 on each second stage buffer 22). Groups of multiple point cells are provided to first stage multiplexers 24 to allow the associated data streams to be directed to selected output ports. The capacitance load on each point cell 23 (which may be simply resistively loaded CML buffers) is reduced by collecting five first stage multiplexers 24 for each second stage multiplexer 25 such that each first stage multiplexer collects eight inputs. The second stage multiplexer 25 also provides signal level conversion; for example, from CML to full swing CMOS.
A cross-point switch such as in FIGS. 1 and 2 may be conveniently implemented using differential current mode logic because of its simplicity, relatively high-speed, low supply noise generation, and high supply noise immunity. But the loads for differential current mode logic circuits are simply resistors, and thus, current mode logic suffers from poor load drive capability and poor speed vs. fan-in (i.e., number of inputs in a gate) trade off. And as data speeds approach and surpass the 1 GHz threshold, circuit reactances create various problems which are not so significant at lower data speeds. In a 32-input multiplexer, the slow down in circuit speed due to delay and rise time would be on the order of 32 times slower than for a simple gate (such as an inverter). And increasing the scale of the input devices provides no speed improvement because the circuit is limited by self-loading.